For technology nodes beyond the 14 nanometer (nm) node the scaling roadmap dictates minimum wiring pitch which is smaller than that which can be printed with lithography techniques which are currently manufacturable, i.e., immersion 193 nm lithography. As advanced lithography techniques such as electron beam (e-beam), extreme UV, or directed self-assembly are not ready for manufacturing, the industry has resorted to so called “pitch split” techniques.
One pitch split technique is sidewall image transfer (SIT), in which mandrel shapes are printed at double the target pitch, and each sidewall of the mandrel shapes is converted into a shape in the target material through a series of processes typically involving sidewall spacer formation. A disadvantage of using SIT processes is that many pattern constructs can not be drawn directly (for example, an odd number of lines, or two parallel lines which do not connect), necessitating a trim process to remove unwanted features. Trimming away features at tight pitch without removing desired features is extremely challenging, requiring excellent overlay tolerance of the trim mask to the SIT patterns, as well as excellent control over the dimension of the mandrel, which controls the exact placement of the SIT patterns.
An alternate pitch split technique involves interleaved exposures, in which the final target pattern is a union of shapes on multiple masks which are not self-aligned. Overlay between the separate exposures then becomes important, as the spacing between adjacent lines at the tightest pitch is directly related to registration between separate lithographic exposures. In practice, controlling the overlay is difficult.
Therefore improved pitch split lithography techniques would be desirable.